1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor device that has a DMOS (diffused metal-oxide semiconductor), a CMOS (complementary metal-oxide semiconductor) and a bipolar transistor on a single substrate, and a method of manufacturing the same.
2. Description of the Related Art
Compact, integrated semiconductor devices can be made cheaper and more reliable by forming several different components on a single substrate. Such integrated devices have many merits, including the reduction of the response time of a circuit and the reduction of the signal transfer time between circuits. Furthermore, very compact, highly integrated circuits are necessary in many fields of research and development, especially for aircraft and space vehicles in which total mass and volume are very constrained for both the vehicle and the payload. More generally, integrated devices are used to manufacture cheaper and more reliable consumer electronics.
FIG. 1 illustrates a conventional semiconductor device which has a bipolar transistor, a DMOS transistor and a CMOS transistor on a single p type substrate 100, defining three corresponding transistor regions, i.e., a bipolar region, a DMOS region and a CMOS region. The substrate 100 is a p- silicon substrate having a plurality of doped regions, insulating layers, and conductors.
The transistor regions have in common the p- substrate 100 and an n type epitaxial layer 120 that is 20 .mu.m thick. The three transistor regions are separated by p+ isolation layers 170 which extend from the surface of the epitaxial layer 120 to the p- substrate 100. The surface of the epitaxial layer 120 is covered with an oxide layer 150 having a plurality of contact holes.
In the bipolar transistor region, an n+ buried layer 110 is formed between the substrate 100 and the epitaxial layer 120, and an n+ sink layer 140 is formed in the epitaxial layer 120 and extends from the surface of the epitaxial layer 120 to the n+ buried layer 110. A p- type base 122 is formed in the epitaxial layer 120, and an n+ emitter 128 and two p+ type bases 127 are formed in the p- type base 122. The oxide layer 150 has contact holes on the emitter 128 and the two p+ bases 127. An emitter electrode E is in contact with the emitter 128, and two base electrodes B are in contact with the two p+ bases 127 through the contact holes.
In the DMOS transistor region, an n+ buried layer 110 is formed between the p-type substrate 100 and the n type epitaxial layer 120. Two p type wells 123 are formed in the n type epitaxial layer 120, and n type sources 124 are formed in the respective p type wells 123. An n+ sink layer 140 is formed in the epitaxial layer 120 and extends from the surface of the epitaxial layer 120 to the n+ buried layer 110, and a drain electrode D is formed thereon. Source electrodes S are formed on the respective sources 124. A gate oxide layer 161 is formed on the surface of the epitaxial layer 120 between the sources 124, and a gate electrode G is formed on the gate oxide layer 161.
The CMOS transistor region is divided into an NMOS region and a PMOS region, and an n channel MOS transistor and a p channel MOS transistor are formed in the respective regions. A p- type well 121 is formed in the n type epitaxial layer 120 of the NMOS transistor region, and n+ type source 125 and drain 126 are formed in the p- type well 121. In the PMOS transistor region, p+ type source 129 and drain 130 are formed in the epitaxial layer 120. Source electrodes S are formed on the sources 125 and 129 and drain electrodes D are formed on the drains 126 and 130. A gate oxide layer 162 is formed on the surface of the p- type well 121, between the source 125 and drain 126 of the NMOS region. Another gate oxide layer 162 is formed on the surface of the epitaxial layer 120 between the source 129 and drain 130 of the PMOS region. Gate electrodes G are formed on the gate oxide layers 162. The gate oxide layers 162 of the CMOS region have the same thickness as the gate oxide layer 161 of the DMOS region since the gate oxide layers 161 and 162 are formed in the same process.
In the conventional semiconductor device shown in FIG. 1, resistance elements are not shown since they are formed in separate steps, making the manufacturing process more complicated.
In addition, the circuit does not have different withstand voltages for the different transistors because the thicknesses of the gate oxide layers in the different region are the same. Therefore the circuits are not reliable when some transistors (e.g., the DMOS transistors) are used at higher operating voltages.